ECE 618: Invited Talk at Feb. 28
Dayane Reis
[Related Papers] (Password request via wjiang8@gmu.edu)
Title
Accelerating Artificial Intelligence with In-Memory Computing: From Applications to Devices
Remote Access
[Zoom] @ 19:20, Feb. 28
Bio
Dayane Reis received her Ph.D. in Computer Science and Engineering from the University of Notre Dame in 2021, where she worked as a Research Assistant in the Hardware-Software Co-design Lab under the direction of Dr. Xiaobo Sharon Hu and Dr. Michael Niemier. She also received the MSc. in Electrical Engineering from the Federal University of Minas Gerais, Brazil, in 2016, and the BSc. in Electronic Engineering from the Pontifical Catholic University of Minas Gerais, Brazil, in 2012. Dayane Reis’ research interests range from hardware-software co-design based on in-memory computing architectures for data-intensive applications to the design of low power, fast, reliable, and secure circuits that make use of emerging (i.e., beyond-CMOS) devices. She is the author of more than 20 articles in journals such as IEEE TVLSI, IEEE TCAD, IEEE Design and Test, as well as renowned conferences including DATE, ISLPED, ICCAD, ASP-DAC, etc. Dayane Reis was one of the winners of the best paper award at the ACM/IEEE International Symposium on Electronics and Low Power Design in 2018 (ISLPED’18) and a recipient of the Cadence Women in Technology (WIT) Scholarship 2018/2019.
Talk Abstract
The advance of Artificial Intelligence (AI) has transformed the society we live in, with broad impacts on several application domains, such as healthcare, bioinformatics, environmental and geological sciences, etc. Three key characteristics of AI applications in the eras of the Internet-of-Things and Big Data are their ubiquitousness, connectivity, and data intensity. In this regard, data intensive applications in AI domains may have their performance limited by the memory bandwidth bottleneck in traditional Von Neumann computer architectures. Memory-bandwidth limited applications can be accelerated by minimizing the data movement between the memory and compute units through in-memory computing (IMC) architectures.
In this talk, I will demonstrate innovative hardware-software codesign approaches based on IMC architectures for accelerating data-intensive machine learning algorithms and, ultimately, AI applications in several domains. These algorithms employ associative searches and nearest neighbor operations to implement the attention mechanism of few-shot learning models, such as Memory Augmented Neural Networks and Prototypical Networks, which can leverage IMC-friendly distance metrics such as L1 (Manhattan) and L∞ (Chebyshev), etc. Hardware kernels for IMC-based hardware-software co-design solutions include memory crossbars, content-addressable memories, configurable memory arrays, and customized sense amplifiers.
The benefit from the IMC-based hardware-software co-design approach can be added up to the low leakage, high density benefits of emerging technologies such as resistive random-access memories, spintronics, ferroelectric-field effect transistors, etc. To this end, the applicability and main characteristics of emerging devices that are amenable to the design of IMC accelerators for AI applications will also be demonstrated. To exemplify, I will walk the audience through a use case of an IMC accelerator for few-shot learning based on ferroelectric-field effect transistors.
